From b2397aae23982b77de29d3a55b263a03852d0714 Mon Sep 17 00:00:00 2001 From: Thomas Munro Date: Fri, 18 Mar 2022 13:40:26 +1300 Subject: [PATCH] Declare aarch64 has single copy atomicity for 8 byte values. Architecture Reference Manual for ARMv8 B2.2.1 [1] For explicit memory effects generated from an Exception level the following rules apply: - A read that is generated by a load instruction that loads a single general-purpose register and is aligned to the size of the read in the instruction is single-copy atomic. - A write that is generated by a store instruction that stores a single general-purpose register and is aligned to the size of the write in the instruction is single-copy atomic. [1] https://documentation-service.arm.com/static/61fbe8f4fa8173727a1b734e https://developer.arm.com/documentation/ddi0487/latest Author: Yura Sokolov Reviewed-by: Thomas Munro Reviewed-by: Alexander Korotkov Discussion: https://postgr.es/m/f7f3f0febe27862711f924a7b0f39e065e547f4b.camel%40postgrespro.ru Discussion: https://postgr.es/m/CA%2BhUKGKyJf7kwYkqDgzTE26Ra1m9nvM%3Deds2RSSu7WSL-r2wKw%40mail.gmail.com --- src/include/port/atomics/arch-arm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/port/atomics/arch-arm.h b/src/include/port/atomics/arch-arm.h index 2083e3230db..9fe8f1b95f7 100644 --- a/src/include/port/atomics/arch-arm.h +++ b/src/include/port/atomics/arch-arm.h @@ -23,4 +23,10 @@ */ #if !defined(__aarch64__) && !defined(__aarch64) #define PG_DISABLE_64_BIT_ATOMICS +#else +/* + * Architecture Reference Manual for ARMv8 states aligned read/write to/from + * general purpose register is atomic. + */ +#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY #endif /* __aarch64__ || __aarch64 */